Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Chapter 8 Theory of Operation
The concept of presenting the shared RAM as a FIFO of packets, with a memory management unit
allocating memory on a per packet basis responds to the following needs:
Memory allocation for receive vs. transmit - A fixed partition between receive and transmit area would not
be efficient. Being able to dynamically allocate it to transmit and receive represents almost the equivalent
of duplicating the memory size for some workstation type of drivers.
Software overhead - By presenting a FIFO of packets, the software driver does not have to waste any time
in calculating pointers for the different buffers that make up different packets. The driver usually deals with
one packet at a time. With this approach, packets are accessible always at the same fixed address, and
access is provided to any byte of the packet.
Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a
block move operation.
Multiple upper layer support - The LAN91C96 facilitates interfacing to multiple upper layer protocols
because of the receive packet processing flexibility. A receive lookahead scheme like ODI or NDIS drivers
is supported by copying a small part of the received packet and letting the upper layer provide a pointer for
the rest of the data. If the upper layer indicates it does not want the packet, it can be removed upon a
single command. If the upper layer wants a specific part of the packet, a block move operation starting at
any particular offset can be done. Out of order receive processing is also supported: if memory for one
packet is not yet available, receive packet processing can continue.
Efficiency - Lacking any level of indirection or linked lists of pointers, virtually all the memory is used for
data. There are no descriptors, forward links and pointers at all. This simplicity and memory efficiency is
accomplished without giving up the benefits of linked lists which is unlimited back-to-back transmission
and reception without CPU intervention for as long as memory is available.
FULL DUPLEX SUPPORT
Full Duplex Ethernet operation refers to the ability of the network (or parts of it) to simultaneously transmit
and receive packets. The CSMA/CD protocol used by Ethernet for accessing a shared medium is
inherently half duplex , and so is the 10BASE-T physical layer where simultaneous transmit and receive
activity is interpreted as a collision.
The LAN91C96 supports two types of Full Duplex operation:
1. Full Duplex mode for diagnostic purposes only, where the received packet is the transmit packet being
looped back. This mode is enabled using the FDUPLX bit in the TCR. In this mode the CSMA/CD
algorithm is used to gain access to the media.
2. FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When the LAN91C96 is
configured for FDSE, its transmit and receive paths will operate independently with Carrier Sense
CSMA/CD function disabled.
Note:
In FDSE mode the packets are not looped back internally.
The loopback (Full Duplex for
Diagnostics(FDUPLX)) function of 10BASE-T transceivers is permanently engaged. It presents the
transmit pair waveform to the receive circuit internally. This function allows the receiver to see the
controller’s own transmission, not only to permit diagnostics, but also to ensure sure that the node defers
to its own transmission - as specified in 802.3.
Behavior in FDSE mode
A) No deferral - The transmit channel is dedicated and always available - The device transmits whenever
it has a packet ready to be sent, while respecting the interframe spacing between transmit packets.
SMSC DS – LAN91C965v&3v
Page 65
Rev. 09/10/2004
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