Non-PCI Single-Chip Full Duplex Ethernet Controller
9.12 Physical Interface
The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T
transceiver. The ENDEC also provides a standard 6-pin AUI interface to an external coax transceiver for
10BASE-2 and 10BASE-5 applications. The internal signals between MAC and the PHY can be routed to
pins by asserting the nXENDEC pin low. This feature allows the interface to an external ENDEC and
transceiver. The PHY functions can be divided into transmit and receive functions.
9.13 Transmit Functions
Manchester Encoding
The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the
selected output driver for transmission over the twisted-pair network or the AUI cable. Data transmission
and encoding is initiated by the Transmit Enable input, TXE, going low.
9.14 Transmit Drivers
The encoded transmit data passes through to the transmit driver pair, TPETXP(N), and its complement,
TPETXDP(N). Each output of the transmit driver pair has a source resistance of 10 ohms maximum and a
current rating of 25 mA maximum. The degree of predistortion is determined by the termination resistors;
the equivalent resistance should be 100 ohms.
Jabber Function
This integrated function prevents the DTE from locking into a continuous transmit state. In 10BASE-T
mode, if transmission continues beyond the specified time limit, the jabber function inhibits further
transmission and asserts the collision indicator nCOLL. The limits for jabber transmission are 20 to 15 ms
in 10BASE-T mode. In the AUI mode, the jabber function is performed by the external transceiver.
SQE Function
In the 10BASE-T mode, the PHY supports the signal quality error (SQE) function. At the end of a
transmission, the PHY asserts the nCOLL signal for 10+/-5 bit times beginning 0.6 to 1.6ms after the last
positive transition of a transmitted frame. In the AUI mode, the SQE function is performed by the external
transceiver.
9.15 Receive Functions
Receive Drivers
Differential signals received off the twisted-pair network or AUI cable are directed to the internal clock
recovery circuit prior to being decoded for the MAC.
Manchester Decoder and Clock Recovery
The PHY performs timing recovery and Manchester decoding of incoming differential signals in 10BASE-T
or AUI modes, with its built-in phase-lock loop (PLL). The decoded (NRZ) data, RXD, and the recovered
clock, RXCLK, becomes available to the MAC, typically within 9 bit times (5 for AUI) after the assertion of
nCRS. The receive clock, RXCLK, is phase-locked to the transmit clock in the absence of a received
signal (idle).
Rev. 11/18/2004
Page 80
SMSC DS – LAN91C96I
DATASHEET
SMSC [ SMSC CORPORATION ]
