Non-PCI Single-Chip Full Duplex Ethernet Controller
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was
successful (when TX_SUC is set). In that case there is no status word associated with its packet number,
and successful packet numbers are not even written into the TX COMPLETION FIFO.
A sequence of transmit packets will only generate an interrupt when the sequence is completely
transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX
INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The packet
number that failed is the present in the FIFO PORTS register, and its pages are not released, allowing the
CPU to restart the sequence after corrective action is taken.
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts
merged into the EPH INT bit. Defaults low (disabled). Writing this bit also serves as the acknowledge by
clearing previous LINK interrupt conditions.
CR ENABLE - Counter Roll over Enable. When set it enables the CTR_ROL bit as one of the interrupts
merged into the EPH INT bit. Defaults low (disabled).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged
into the EPH INT bit. Defaults low (disabled). Transmit Error is any condition that clears TXENA with
TX_SUC staying low as described in the EPHSR register.
EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE
refers to. When high, the General Purpose Register is the only register read or written. When low, the
RELOAD and STORE functions are enabled.
RELOAD
The LAN91C96I reads the Configuration, Base and Individual Address, and STORE writes the
Configuration and Base registers.
Also when set it will read the EEPROM and update relevant registers with its contents. This bit then Clears
upon completing the operation.
STORE
The STORE LAN91C96I bit when set, stores the contents of all relevant registers in the serial EEPROM.
This bit is cleared upon completing the operation.
Note:
When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high. The
remaining 14 bits of this register will be invalid. During this time, attempted read/write operations, other
than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume
accesses to the LAN91C96I after both bits are low. A worst case RELOAD operation initiated by RESET
or by software takes less than 750usec in either mode.
Rev. 11/18/2004
Page 46
SMSC DS – LAN91C96I
DATASHEET
SMSC [ SMSC CORPORATION ]
