10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
PIN NO.
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
TQFP
QFP
42
44
Local Bus Clock LCLK
I**
Input. Used to interface synchronous
buses. Maximum frequency is 50 MHz.
Limited to 8.33 MHz for EISA DMA burst
mode. This pin should be tied high if it is
in asynchronous mode.
38
40
Asynchronous
Ready
ARDY
OD16
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the
XTAL1 clock and, therefore,
asynchronous to the host CPU or bus
clock. ARDY is negated during
Asynchronous cycle when one of the
following conditions occurs:
No_Wait Bit in the Configuration Register
is cleared.
Read FIFO contains less than 4 bytes
when read.
Write FIFO is full when write.
43
45
nSynchronous
Ready
nSRDY
O16
Output. This output is used when
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This
signal remains normally inactive, and its
falling edge indicates completion. This
signal is synchronous to the bus clock
LCLK.
46
29
48
31
nReady Return nRDYRTN I**
Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK
edges, and synchronous cycles are
delayed until it is sampled high.
Interrupt
INTR0
nLDEV
O24
O16
Interrupt Output – Active High, it’s used to
interrupt the Host on a status event.
Note: The selection bits used to
determined by the value of INT SEL 1-0
bits in the Configuration Register are no
longer required and have been set to
reserved in this revision of the FEAST
family of devices.
45
47
nLocal Device
Output. This active low output is asserted
when AEN is low and A4-A15 decode to
the LAN91C111 address programmed
into the high byte of the Base Address
Register. nLDEV is a combinatorial
decode of unlatched address and AEN
signals.
31
32
34
33
34
36
nRead Strobe
nWrite Strobe
nRD
IS**
IS**
Input. Used in asynchronous bus
interfaces.
nWR
Input. Used in asynchronous bus
interfaces.
nData Path
Chip Select
nDATACS
I with
Input. When nDATACS is low, the Data
Path can be accessed regardless of the
values of AEN, A1-A15 and the content of
the BANK SELECT Register. nDATACS
provides an interface for bursting to and
from the LAN91C111 32 bits at a time.
pullup**
Revision 1.8 (07-13-05)
SMSC LAN91C111-REV B
DATA2S4HEET
SMSC [ SMSC CORPORATION ]
