10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
MII External
Signals
RBIAS
EEPROM
100BASE-TX
CONTROL
TRANSMITTER
SWITCHED
+
-
TPO+
TPO-
4B5B
ENCODER
LP
FILTER
MLT3
SCRAMBLER
CURRENT
SOURCE
ENCODER
TXD[3:0]
TX_ER
TXEN100
TX25
CLOCK
GEN
(PLL)
10BASE-T
TRANSMITTER
+
-
DAC
LP
MANCHESTER
ROM
FILTER
CLOCK
GEN
CRS100
COL100
COLLISION
(PLL)
RXD[3:0]
RX_ER
RX_DV
RX25
100BASE-TX
RECEIVER
SQUELCH
CLOCK &
+/- Vth
+
+
-
TPI+
TPI-
4B5B
DECODER
ADAPTIVE
MLT
DESCRAMBL
ER
DATA
EQUALIZER
ENCODER
RECOVERY
AUTO
NEGOTIATION
& LINK
MII
MDI
MCLK
MDO
SERIAL
Manage
-ment
10BASE-T
RECEIVER
SQUELCH
+/- Vth
+
+
-
MII
CLOCK &
DATA
LP
FILTER
Recovery
(Manchester
Decoder)
Multiplexer
LEDA
S
D
1
S
8
Power
nPLED[0-5]
LS[2-0]A
PHY
CONTROLS
EN
B
AUTONEG
LOGIC
C
C
C
3
1
2
On
Reset
Multiplexer
S
D
1
LEDB
LED
S
8
Control
EN
B
C
C
C
3
1
2
LS[2-0]B
Figure 3.3 - LAN91C111 Physical Layer to Internal MAC Block Diagram
Rev. 1.4 (12-12-03)
Page 12
SMSC LAN91C111 Rev. B
DATASHEET
SMSC [ SMSC CORPORATION ]
