10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
EEPROM
MII
INTERFACE
Control
Control
Control
Control
Control
Control
Arbiter
8-32 bit
Bus
TPO
Ethernet
Protocol
Handler
(EPH)
10/100
PHY
Interface
Unit
Address
Control
MMU
TX/RX
FIFO
DMA
Pointer
TX Data
RX Data
TXD[0-3]
RXD[0-3]
WR
32-bit Data
32-bit Data
FIFO
8K Byte
Dynamically
Allocated
SRAM
TPI
Data
RD
FIFO
Figure 3.2 - Block Diagram
The diagram shown in Figure 3.2 describes the supported Host interfaces, which include ISA or Generic
Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and
8 bit embedded RISC and ARM processors.
The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a
10/100 Ethernet Physical layer framer to the internal MAC.
SMSC LAN91C111 Rev. B
Page 11
Rev. 1.4 (12-12-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
