Table 5 - EISA 32 Bit Slave Signal Connections
EISA BUS
SIGNAL
LAN91C100 SIGNAL
D0-D31
NOTES
D0-D31
32 bit data bus. The bus byte(s) used to access the
device are a function of nBE0-nBE3:
nBE nBE nBE nBE
0
1
2
3
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
1
1
0
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied
low in this application. Other combinations of nBE are
not supported by the LAN91C100. S/W drivers are not
anticipated to generate them.
nEX32
nNOWS
(optional
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid
decodes of the LAN91C100's pins A15-A4 and AEN=0.
nNOWS is similar to nLDEV except that it should go
inactive on nSTART rising. nNOWS can be used to
request compressed cycles (1.5 BCLK long, nRD/nWR
will be 1/2 BCLK wide).
additional logic)
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK
LCLK
EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK<n>
nDATACS
DMA Acknowledge. Active during Slave DMA cycles.
Used by the LAN91C100 as nDATACS direct access to
data path.
nIORC
W/nR
Indicates the direction and timing of the DMA cycles.
High during LAN91C100 writes; low during LAN91C100
reads.
nIOWC
nCYCLE
Indicates slave DMA writes.
nEXRDY
nRDYRTN
EISA bus signal indicating whether a slave DMA cycle
will take place on the next BCLK rising edge, or should
be postponed. nRDYRTN is used as an input in the slave
77
SMSC [ SMSC CORPORATION ]
