APPLICATION CONSIDERATIONS
The LAN91C100 is envisioned to fit a few
e) 100 Mbps MII compliant PHY
f) Some bus specific glue logic
different bus types. This section describes the
basic guidelines, system level implications and
sample configurations for the most relevant bus
types. All applications are based on buffered
architectures with a private SRAM bus.
Target systems:
a) VL Local Bus 32 bit systemsa)
Local Bus 32 bit systems) VL
VL
Local
Local
Bus 32 bit systems)
Bus 32 bit systems
VL
FAST ETHERNET SLAVE ADAPTER
Slave non-intelligent board implementing 100
Mbps and 10 Mbps speeds.
b) High-end ISA machines
c) EISA 32 bit slave
Adapter requires:
VL Local Bus 32 Bit Systems
a) LAN91C100 Fast Ethernet Controller
b) Four SRAMs (32k x 8 - 25ns)
c) Serial EEPROM (93C46)
On VL Local Bus and other 32 bit embedded
systems, the LAN91C100 is accessed as a 32
bit peripheral in terms of the bus interface. All
registers except the DATA REGISTER will be
accessed using byte or word instructions.
Accesses to the DATA REGISTER could use
byte, word, or dword instructions.
d) 10 Mbps ENDEC and transceiver chip
Table 3 - VL Local Bus Signal Connections
LAN91C100
SIGNAL
VL BUS
SIGNAL
NOTES
A2-A15
M/nIO
W/nR
A2-A15
AEN
Address bus used for I/O space and register decoding,
latched by nADS rising edge, and transparent on nADS low
time
Qualifies valid I/O decoding - enabled access when low.
This signal is latched by nADS rising edge and transparent
on nADS low time
W/nR
Direction of access. Sampled by the LAN91C100 on first
rising clock that has nCYCLE active. High on writes, low on
reads.
nRDYRTN
nLRDY
nRDYRTN
Ready return. Direct connection to VL bus.
nSRDY
and some logic
nSRDY has the appropriate functionality and timing to
create the VL nLRDY except that nLRDY behaves like an
open drain output most of the time.
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SMSC [ SMSC CORPORATION ]
