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LAN91C100FD-FD-SS 参数 Datasheet PDF下载

LAN91C100FD-FD-SS图片预览
型号: LAN91C100FD-FD-SS
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC]
分类和应用: 控制器以太网
文件页数/大小: 101 页 / 347 K
品牌: SMSC [ SMSC CORPORATION ]
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BOARD SETUP INFORMATION  
The following parameters are obtained from the  
EEPROM as board setup information:  
REGISTER  
EEPROM WORD  
ADDRESS  
Configuration  
Register  
IOS Value * 4  
ETHERNET INDIVIDUAL ADDRESS  
I/O BASE ADDRESS  
10BASE-T or AUI INTERFACE  
MII or ENDEC INTERFACE  
INTERRUPT LINE SELECTION  
Base Register  
(IOS Value * 4) + 1  
INDIVIDUAL ADDRESS  
20-22 hex  
All the above mentioned values are read from  
the EEPROM upon hardware reset. Except for  
the INDIVIDUAL ADDRESS, the value of the  
IOS switches determines the offset within the  
EEPROM for these parameters, in such a way  
that many identical boards can be plugged into  
the same system by just changing the IOS  
jumpers.  
If IOS2-0 = 7 , only the INDIVIDUAL ADDRESS  
is read from the EEPROM. Currently assigned  
values are assumed for the other registers.  
These values are default if the EEPROM read  
operation follows hardware reset.  
The EEPROM SELECT bit is used to determine  
the type of EEPROM operation: a) normal or b)  
general purpose register.  
In order to support a software utility based  
installation, even if the EEPROM was never  
programmed, the EEPROM can be written using  
the LAN91C100. One of the IOS combination is  
associated with a fixed default value for the key  
parameters (I/O BASE, INTERRUPT) that can  
always be used regardless of the EEPROM  
based value being programmed. This value will  
be used if all IOS pins are left open or pulled  
high.  
a) NORMAL  
EEPROM  
OPERATION  
-
EEPROM SELECT bit = 0  
On EEPROM read operations (after reset or  
after setting RELOAD high) the  
CONFIGURATION REGISTER and BASE  
REGISTER are updated with the EEPROM  
values at locations defined by the IOS2-0 pins.  
The INDIVIDUAL ADDRESS registers are  
updated with the values stored in the  
INDIVIDUAL ADDRESS area of the EEPROM.  
The EEPROM is arranged as a 64 x 16 array.  
The specific target device is the 9346 1024-bit  
Serial EEPROM. All EEPROM accesses are  
done in words. All EEPROM addresses in the  
spec are specified as word addresses.  
68  
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