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LAN91C100FD-FD-SS 参数 Datasheet PDF下载

LAN91C100FD-FD-SS图片预览
型号: LAN91C100FD-FD-SS
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC]
分类和应用: 控制器以太网
文件页数/大小: 101 页 / 347 K
品牌: SMSC [ SMSC CORPORATION ]
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AUTO RELEASE  
-
When set, successful  
TX INT will be set on a fatal transmit error  
allowing the CPU to know that the transmit  
process has stopped and therefore the FIFO will  
not be emptied.  
transmit packets are not written into completion  
FIFO, and their memory is released  
automatically.  
1) One interrupt per packet: enable TX INT,  
set AUTO RELEASE=0. The software driver  
can find the completion result in memory and  
process the interrupt one packet at a time.  
Depending on the completion code the driver  
will take different actions. Note that the transmit  
process is working in parallel and other  
This mode has the advantage of a smaller CPU  
overhead, and faster memory de-allocation.  
Note that when AUTO RELEASE=1 the CPU is  
not provided with the packet numbers that  
completed successfully.  
Note: The pointer register is shared by any  
process accessing the LAN91C100 memory. In  
order to allow processes to be interruptable, the  
interrupting process is responsible for reading  
the pointer value before modifying it, saving it,  
and restoring it before returning from the  
interrupt.  
transmissions might be taking place.  
The  
LAN91C100 is virtually queuing the packet  
numbers and their status words.  
In this case, the transmit interrupt service  
routine can find the next packet number to be  
serviced by reading the TX DONE PACKET  
NUMBER at the FIFO PORTS register. This  
eliminates the need for the driver to keep a list  
of packet numbers being transmitted. The  
numbers are queued by the LAN91C100 and  
provided back to the CPU as their transmission  
completes.  
Typically there would be three processes using  
the pointer:  
1) Transmit loading (sometimes interrupt  
driven)  
2) Receive unloading (interrupt driven)  
3) Transmit Status reading (interrupt driven).  
2) One interrupt per sequence of packets:  
Enable TX EMPTY INT and TX INT, set AUTO  
RELEASE=1. TX EMPTY INT is generated only  
after transmitting the last packet in the FIFO.  
1) and 3) also share the usage of the Packet  
Number Register. Therefore saving and  
restoring the PNR is also required from interrupt  
service routines.  
65  
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