I/O SPACE - BANK1
OFFSET
NAME
TYPE
SYMBOL
CTR
C
CONTROL REGISTER
READ/WRITE
HIGH
BYTE
0
0
RCV_BAD
0
0
AUTO
RELEASE
0
0
0
X
X
0
X
X
LOW
BYTE
LE
ENABLE
CR
ENABLE
TE
ENABLE
EEPROM
SELECT
RELOAD
0
STORE
0
0
0
0
X
0
RCV_BAD When set, bad CRC packets are
received. When clear bad CRC packets do not
generate interrupts and their memory is
released.
CR ENABLE Counter Roll over Enable. When
set it enables the CTR_ROL bit as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled).
AUTO RELEASE When set, transmit pages are
released by transmit completion if the
transmission was successful (when TX_SUC is
set). In that case there is no status word
associated with its packet number, and
successful packet numbers are not even written
into the TX COMPLETION FIFO. A sequence of
transmit packets will only generate an interrupt
when the sequence is completely transmitted
(TX EMPTY INT will be set), or when a packet in
the sequence experiences a fatal error (TX INT
will be set). Upon a fatal error TXENA is
cleared and the transmission sequence stops.
The packet number that failed is the present in
the FIFO PORTS register, and its pages are not
released, allowing the CPU to restart the
sequence after corrective action is taken.
TE ENABLE Transmit Error Enable. When set
it enables Transmit Error as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Transmit Error is any condition
that clears TXENA with TX_SUC staying low as
described in the EPHSR register.
EEPROM SELECT This bit allows the CPU to
specify which registers the EEPROM RELOAD
or STORE refers to. When high, the General
Purpose Register is the only register read or
written.
When low, RELOAD reads
Configuration, Base and Individual Address, and
STORE writes the Configuration and Base
registers.
RELOAD When set, it will read the EEPROM
and update relevant registers with its contents.
Clears upon completing the operation.
LE ENABLE Link Error Enable. When set it
enables the LINK_OK bit transition as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Writing this bit also serves as the
acknowledge by clearing previous LINK interrupt
conditions.
STORE When set, stores the contents of all
relevant registers in the serial EEPROM. Clears
upon completing the operation.
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SMSC [ SMSC CORPORATION ]
