I/O SPACE - BANK 0
OFFSET
NAME
TYPE
SYMBOL
EPHSR
2
EPH STATUS REGISTER
READ ONLY
This register stores the status of the last frame transmitted. This register value, upon individual
transmit packet completion, is stored as the first word in the memory area allocated to the packet.
Packet interrupt processing should use the copy in memory as the register itself will be updated by
subsequent packet transmissions. The register can be used for real time values (like TXENA and
LINK OK). If TXENA is cleared the register holds the last packet completion status.
HIGH
BYTE
TX UNRN
0
LINK_OK RX_OVRN CTR_ROL EXC_DEF
LOST
CARR
LATCOL
0
-nLNK Pin
0
0
0
0
X
LOW
BYTE
TX DEFR
0
LTX BRD
0
SQET
0
16COL
0
LTX MULT MUL COL
SNGL
COL
TX_SUC
0
0
0
0
TXUNRN Transmit Under Run. Set if under run
occurs, it also clears TXENA bit in TCR.
Cleared by setting TXENA high. This bit should
never be set under normal operation.
EXC_DEF
Excessive Deferral.
When set
last/current transmit was deferred for more than
1518 * 2 byte times. Cleared at the end of every
packet sent.
LINK_OK General purpose input port driven by
nLNK pin inverted. Typically used for LINK
Test. A transition on the value of this bit
generates an interrupt.
LOST_CARR Lost Carrier Sense. When set,
indicates that Carrier Sense was not present at
end of preamble. Valid only if MON_CSN is
enabled. This condition causes TXENA bit in
TCR to be reset. Cleared by setting TXENA bit
in TCR.
RX_OVRN Upon FIFO overrun, the receiver
asserts this bit and clears the FIFO. The
receiver stays enabled. After a valid preamble
has been detected on a subsequent frame,
RX_OVRN is de-asserted. The RX_OVRN INT
bit in the Interrupt Status Register will also be
set and stay set until cleared by the CPU. Note
that receive overruns could occur only if receive
memory allocations fail.
LATCOL Late collision detected on last transmit
frame. If set, a late collision was detected (later
than 64 byte times into the frame). When
detected, the transmitter JAMs and turns itself
off, clearing the TXENA bit in TCR. Cleared by
setting TXENA in TCR.
TX_DEFR
Transmit Deferred.
When set,
CTR_ROL Counter Roll Over. When set, one
or more 4-bit counters have reached maximum
carrier was detected during the first 6.4 sec of
the inter frame gap. Cleared at the end of every
m
count (15).
register.
Cleared by reading the ECR
packet sent.
LTX_BRD Last transmit frame was a broadcast.
24
SMSC [ SMSC CORPORATION ]
