by this block which, under CPU command, will
program specific locations in the EEPROM.
This block is an autonomous state machine, and
it controls the LAN91C100's internal Data Bus
during active operation.
Serial EEPROM Interface Block
This block is responsible for reading the serial
EEPROM upon hardware reset (or equivalent
command) and defining defaults for some key
registers. A write operation is also implemented
EEPROM
EEPROM
INTERFACE
DATA BUS
ADDRESS
TRANSMIT
RECEIVE
RX
FIFO
TX
FIFO
BUS
DMA
CSMA/CD
BUS INTERFACE
CONTROL
TX
COMPL
FIFO
ARBITER
WRITE
READ
DATA
REG
DATA
REG
MMU
DATA
ADDRESS
BUFFER RAM
FIGURE 3 - LAN91C100 INTERNAL BLOCK DIAGRAM WITH DATA PATH
17
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