combination of bytes, word, or doublewords.
The Arbiter will indicate 'Not Ready' whenever a
cycle is initiated that cannot be satisfied by the
present state of the FIFO.
determined by using nSRDY.
controlled by LCLK and is synchronous to the
bus.
nSRDY is
Direct 32-bit access to the Data Path is
supported by using the nDATACS input. By
asserting nDATACS, external DMA-type of
devices will bypass the BIU address decoders
and can sequentially access memory with no
CPU intervention. nDATACS accesses can be
used in the DMA burst mode (nVLBUS=1) or in
asynchronous cycles. These cycles MUST be
32-bit cycles. Please refer to the corresponding
timing diagrams for details on these cycles.
The depth of the FIFOs will accommodate the
worst case arbitration and byte access
alignment pattern while still preserving the CPU
cycle time when accessing the Data Register.
MMU Block
The Hardware Memory Management Unit is
similar to the LAN91C90's MMU.
It does
dynamic memory allocation and queuing of
transmit and receive packets, and it determines
the value of the transmit and receive interrupts
as a function of the queues. The page size is
still 2k, and with a maximum memory size of
128k the MMU uses 64x6 FIFOs. MIR and MCR
values are interpreted in 512 byte units.
MAC-PHY Interface
Two separate interfaces are defined; one for the
10 Mbps bit rate interface and one for the MII
100 Mbps and 10 Mbps nibble rate interface.
The 10 Mbps ENDEC interface comprises the
signals used for interfacing Ethernet ENDECs.
The 100 Mbps interface follows the MII draft
standard for 100 Mbps 802.3 networks, and it is
based on transferring nibbles between the MAC
and the PHY.
BIU Block
The Bus Interface Unit can handle synchronous
as well as asynchronous buses; different signals
are used for each one. Transparent latches are
added on the address path using rising nADS
for latching.
For the MII interface, transmit data is clocked
out using the TX25 clock input, while receive
data is clocked in using RX25.
When working with an asynchronous bus like
ISA, the read and write operations are controlled
by the edges of nRD and nWR. ARDY is used
for notifying the system that it should extend the
access cycle. The leading edge of ARDY is
generated by the leading edge of nRD or nWR
while the trailing edge of ARDY is controlled by
the LAN91C100's internal clock and, therefore,
is asynchronous to the bus.
Switching between the ENDEC and MII
interfaces is controlled by the MII Select bit in
the Configuration Register. The MIISEL pin
reflects the value of the bit and may be used to
control external multiplexing logic.
MII Management Interface Block
PHY management through the MII management
interface is supported by the LAN91C100 by
providing the means to drive a tri-statable data
output, a clock, and reading an input. Timing
and framing for each management command is
be generated by the CPU.
In the synchronous VL Bus type mode, nCYCLE
and LCLK are used for read and write
operations. Completion of the cycle may be
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