High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.20
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
Offset:
A4h
Size:
32 bits
This register is used to control the read and write operations with the MAC CSR’s
BITS
DESCRIPTION
TYPE
DEFAULT
31
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
SC
0
30
R/nW. When set, this bit indicates that the host is requesting a read
R/W
0
operation. When clear, the host is performing a write.
29-8
7-0
Reserved.
RO
-
CSR Address. The 8-bit value in this field selects which MAC CSR will be
R/W
00h
accessed with the read or write operation.
5.3.21
MAC_CSR_DATA – MAC CSR Synchronizer Data Register
Offset:
A8h
Size:
32 bits
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write
operations with the MAC CSR’s
BITS
DESCRIPTION
TYPE
DEFAULT
31-0
MAC CSR Data. Value read from or written to the MAC CSR’s.
R/W
00000000h
SMSC LAN9117
Revision 1.1 (05-17-05)
DATA9S1HEET
SMSC [ SMSC CORPORATION ]
