High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.18
FREE_RUN—Free-Run 25MHz Counter
Offset:
9Ch
Size:
32 bits
This register reflects the value of the free-running 25MHz counter.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Free Running SCLK Counter (FR_CNT):
RO
-
Note:
This field reflects the value of a free-running 32-bit counter. At reset
the counter starts at zero and is incremented for every 25MHz
cycle. When the maximum count has been reached the counter will
rollover. Since the bus interface is 16-bits wide, and this is a 32-
bit counter, the count value is latched on the first read. The
FREE_RUN counter can take up to 160nS to clear after a reset
event.
Note:
This counter will run regardless of the power management states
D0, D1 or D2.
5.3.19
RX_DROP– Receiver Dropped Frames Counter
Offset:
A0h
Size:
32 bits
This register indicates the number of receive frames that have been dropped.
BITS
DESCRIPTION
TYPE
RC
DEFAULT
31-0
RX Dropped Frame Counter (RX_DFC). This counter is incremented every
time a receive frame is dropped. RX_DFC is cleared on any read of this
register.
00000000h
An interrupt can be issued when this counter passes through its halfway
point (7FFFFFFFh to 80000000h).
Revision 1.1 (05-17-05)
SMSC LAN9117
DATA9S0HEET
SMSC [ SMSC CORPORATION ]
