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LAN9117-MT 参数 Datasheet PDF下载

LAN9117-MT图片预览
型号: LAN9117-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能单芯片10/100非PCI以太网控制器 [HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER]
分类和应用: 外围集成电路数据传输控制器PC局域网以太网局域网(LAN)标准以太网:16GBASE-T通信时钟
文件页数/大小: 131 页 / 1539 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller  
Datasheet  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
12  
11  
Reserved  
RO  
-
TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data  
R/WC  
0
FIFO underruns.  
10  
9
TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data  
R/WC  
R/WC  
R/WC  
R/WC  
R/WC  
R/WC  
R/WC  
R/WC  
R/WC  
0
0
FIFO is full, and another write is attempted.  
TX Data FIFO Available Interrupt (TDFA). Generated when the TX data  
FIFO available space is greater than the programmed level.  
8
TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status  
0
FIFO is full.  
7
TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status  
0
FIFO reaches the programmed level.  
6
RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued  
0
whenever a receive frame is dropped.  
5
RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO  
0
reaches the programmed level.  
4
RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status  
0
FIFO is full.  
3
RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status  
0
FIFO reaches the programmed level.  
2-0  
GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.  
000  
These interrupts are configured through the GPIO_CFG register.  
5.3.4  
INT_EN—Interrupt Enable Register  
Offset:  
5Ch  
Size:  
32 bits  
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the  
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of  
the interrupt source regardless of whether the source is enabled as an interrupt in this register.  
BITS  
31  
DESCRIPTION  
TYPE  
R/W  
DEFAULT  
Software Interrupt (SW_INT_EN)  
Reserved  
0
-
30:26  
25  
RO  
R/W  
R/W  
R/W  
TX Stopped Interrupt Enable (TXSTOP_INT_EN)  
RX Stopped Interrupt Enable (RXSTOP_INT_EN)  
0
0
0
24  
23  
RX Dropped Frame Counter Halfway Interrupt Enable  
(RXDFH_INT_EN).  
22  
21  
20  
19  
Reserved  
RO  
R/W  
R/W  
R/W  
0
0
0
0
TX IOC Interrupt Enable (TIOC_INT_EN)  
RX DMA Interrupt (RXD_INT).  
GP Timer (GPT_INT_EN)  
Revision 1.1 (05-17-05)  
SMSC LAN9117  
DATA7S6HEET  
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