High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.1 LAN9117 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
SYMBOL
REGISTER NAME
DEFAULT
ACh
B0h
AFC_CFG
E2P_CMD
Automatic Flow Control Configuration
00000000h
00000000h
EEPROM command (The EEPROM is
indexed through this register)
B4h
E2P_DATA
EEPROM Data
00000000h
-
B8h - FCh
RESERVED
Reserved for future use
5.3.1
ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
BITS
31-16
15-0
DESCRIPTION
TYPE
RO
DEFAULT
0117h
Chip ID. This read-only field identifies this design
Chip Revision. This is the current revision of the chip.
RO
0001h
5.3.2
IRQ_CFG—Interrupt Configuration Register
Offset:
54h
Size:
32 bits
This register configures and indicates the state of the IRQ signal.
BITS
DESCRIPTION
TYPE
R/W
DEFAULT
31:24
Interrupt Deassertion Interval (INT_DEAS). This field determines the
Interrupt Deassertion Interval for the Interrupt Request in multiples of 10
microseconds.
0
Writing zeros to this field disables the INT_DEAS Interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-
zero value is written to the INT_DEAS field, any subsequent interrupts
will obey the new setting.
Note:
The Interrupt Deassertion interval does not apply to the PME
interrupt.
23-15
Reserved
RO
-
SMSC LAN9117
Revision 1.1 (05-17-05)
DATA7S3HEET
SMSC [ SMSC CORPORATION ]
