High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
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Set EXT_PHY_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to
the desired MII port. This step switches the RXD[3:0], RX_DV, RX_ER, TXD[3:0], TX_EN, CRS
and COL signals to the desired port.
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Set PHY_CLK_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to
the desired port. This must be the same port that is selected by EXT_PHY_SEL.
The host must wait a period of time of not less than 5 cycles of the slowest, newly enabled clock
before executing the next step in this procedure.
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Enable theLAN9117 transmitter.
Enable the LAN9117 receiver.
The process is complete. The LAN9117 is now operational using the newly selected MII device.
The above procedure must be repeated each time the MII port is switched. The procedure is identical
when switching from internal PHY to external MII, or vice-versa.
Revision 1.1 (05-17-05)
SMSC LAN9117
DATA4S4HEET
SMSC [ SMSC CORPORATION ]
