High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
3.11.1
Power-On Reset (POR)
A Power-On reset occurs whenever power is initially applied to the LAN9117, or if power is removed
and reapplied to the LAN9117. A timer within the LAN9117 will assert the internal reset for
approximately 22ms. The READY bit in the PMT_CTRL register can be read from the host interface
and will read back a ‘0’ until the POR is complete. Upon completion of the POR, the READY bit in
PMT_CTRL is set high, and the LAN9117 can be configured via its control registers.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal
reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
3.11.2
Hardware Reset Input (nRESET)
A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the
PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware
reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high.
After the “READY” bit is set, the LAN9117 can be configured via its control registers. The nRESET
signal is pulled-high internally by the LAN9117 and can be left unconnected if unused. If used, nRESET
must be driven low for a minimum period as defined in Section 6.8, "Reset Timing," on page 124.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
3.11.3
Resume Reset Timing
After issuing a write to the BYTE_TEST register to wake the LAN9117 from a power-down state, the
READY bit in PMT_CTRL will assert (set High) within 2ms.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
3.11.4
Soft Reset (SRST)
Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will
return to ‘0’ after approximately 2 µs, at which time the Soft Reset is complete. Soft reset does not
clear control register bits marked as NASR.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,
(within 2µs). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
3.11.5
PHY Reset Timing
The following sections and tables specify the operation and time required for the internal PHY to
become operational after various resets or when returning from the reduced power state.
3.11.5.1
3.11.5.2
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This
self-clearing bit will return to ‘0’ after approximately 100 µs, at which time the PHY reset is complete.
PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register.
This self-clearing bit will return to ‘0’ at which time the PHY reset is complete.
Revision 1.1 (05-17-05)
SMSC LAN9117
DATA4S2HEET
SMSC [ SMSC CORPORATION ]
