High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.1 Host Bus Interface Signals
BUFFER
#
PIN NO.
NAME
SYMBOL
TYPE
PINS
DESCRIPTION
43-46,49-
53,56-59,62-
64
Host Data
D[15:0]
I/O8
16
Bi-directional data port. Supports
Big/Little Endian Byte ordering.
12-18
Host Address
Read Strobe
Write Strobe
A[7:1]
nRD
IS
IS
IS
7
1
1
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
92
Active low strobe to indicate a read
cycle.
93
nWR
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9117
when it is in a reduced power state.
94
72
Chip Select
nCS
IRQ
IS
1
1
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9117 when it is in a
reduced power state.
Interrupt
Request
O8/OD8
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
71,73,84,90,
91
Reserved
Reserved
5
1
No Connect
74
10/100
SPEED_SEL
I (PU)
This signal functions as a configuration
input on power-up and is used to select
the default Ethernet settings. Upon
deassertion of reset, the value of the
input is latched. This signal functions
as shown in Table 2.2, "Default
Selector
Ethernet Settings", below.
76
FIFO Select
FIFO_SEL
IS
1
When driven high all accesses to the
LAN9117 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
DUPLEX
SPEED_SEL
SPEED
10MBPS
100MBPS
AUTO NEG.
DISABLED
ENABLED
0
1
HALF-DUPLEX
HALF-DUPLEX
SMSC LAN9117
Revision 1.1 (05-17-05)
DATA1S5HEET
SMSC [ SMSC CORPORATION ]
