Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Additionally, please refer to Section 5.3.17, "ENDIAN—Endian Control," on page 84 for additional
information on status indication on Endian modes.
Table 3.7 Byte Lane Mapping
DATA PINS
MODE OF
OPERATION
D[31:24]
D[23:16]
D[15:8]
D[7:0]
DESCRIPTION
32-bit
Byte 3
(MSB)
Byte 2
Byte 1
Byte 0
(LSB)
This is the native mode of the LAN9116.
Endianess does not matter when both
WORD lanes are in operation.
Mode 0 (Big Endian Register equal to 0xFFFFFFFF)h
A1 = 0
A1 = 1
--
--
--
--
Byte 3
Byte 1
Byte 2
Byte 0
Note:
Note:
This mode can be used by 32-
bit processors operating with
an external 16-bit bus.
Mode 1 (Big Endian Register not equal to 0xFFFFFFFF)h
A1 = 0
A1 = 1
--
--
--
--
Byte 1
Byte 3
Byte 0
Byte 2
This mode can also be used
by native 16-bit processors.
3.8
General Purpose Timer (GP Timer)
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_CNT field is initialized to FFFFh. The GPT_CNT register is also initialized
to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any time; e.g.,
before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in the
GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
3.9
EEPROM Interface
LAN9116 can optionally load its MAC address from an external serial EEPROM. If a properly
configured EEPROM is detected by LAN9116 at power-up, hard reset or soft reset, the ADDRH and
ADDRL registers will be loaded with the contents of the EEPROM. If a properly configured EEPROM
is not detected, it is the responsibility of the host LAN Driver to set the IEEE addresses.
The LAN9116 EEPROM controller also allows the host system to read, write and erase the contents
of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for
128 x 8-bit operation.
Revision 1.1 (05-17-05)
SMSC LAN9116
DATA3S0HEET
SMSC [ SMSC CORPORATION ]
