Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9116 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
3.6
32-bit vs. 16-bit Host Bus Width Operation
The LAN9116 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus.
An external strap is used to select between the two modes. 32-bit mode is the native environment for
the LAN9116 Ethernet controller and no special requirements exist for communication in this mode.
However, when this part is used in the 16-bit mode, two writes or reads must be performed back to
back to properly communicate.
The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the “Hardware
Configuration Register”. Please refer to Section 5.3.9, "HW_CFG—Hardware Configuration Register,"
on page 75 for additional information on this register.
3.6.1
3.6.2
16-bit Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9116 disregards the transfer.
16-bit Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9116 will reset its read counters and restart a new cycle on the next read. The Upper 16 data pins
(D[31:16]) are not driven by the LAN9116 in 16-bit mode. These pins have internal pull-down’s and the
signals are left in a high-impedance state.
3.7
Big and Little Endian Support
The SMSC LAN9116 supports “Big-” or “Little-Endian” processors in either 16 or 32-bit bus width
modes. To support big-endian processors, the hardware designer must explicitly invert the layout of
the byte lanes. In addition, for a 16-bit interface, the big-endian register must be set correctly following
Table 3.7, "Byte Lane Mapping".
The host bus interface can be selected via an external strap to translate the data bus into either mode.
Please refer to Table 2.4, “Serial EEPROM Interface Signals,” on page 16, for information on
multiplexed signal D32/nD16 for more information on data bus width selection.
SMSC LAN9116
Revision 1.1 (05-17-05)
DATA2S9HEET
SMSC [ SMSC CORPORATION ]
