±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
4.13.1
Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN8700/LAN8700i and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will
be read as hexadecimal “FFFF”.
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and
MDC is the clock.
A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the
SMI packet causing the PHY to respond to any address. This feature is useful in multi-PHY
applications and in production testing, where the same register can be written in all the PHYs using a
single write transaction.
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO
signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the
SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between
edges.
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 4.6 and Figure 4.7.
The timing relationships of the MDIO signals are further described in Section 6.1, "Serial Management
Interface (SMI) Timing," on page 57.
Read Cycle
MDC
MDI0
...
D1
D15 D14
D0
32 1's
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
...
Start of
Frame
OP
Code
Turn
Around
Preamble
PHY Address
Register Address
Data
Data To Phy
Data From Phy
Figure 4.6 MDIO Timing and Frame Structure - READ Cycle
Write Cycle
MDC
...
D15 D14
D1
D0
32 1's
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address Register Address
...
MDIO
Start of
Frame
OP
Code
Turn
Around
Preamble
Data
Data To Phy
Figure 4.7 MDIO Timing and Frame Structure - WRITE Cycle
Revision 2.3 (04-12-11)
SMSC LAN8700/LAN8700i
DATA3S4HEET
SMSC [ SMSC CORPORATION ]
