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LAN8700C-AEZG 参数 Datasheet PDF下载

LAN8700C-AEZG图片预览
型号: LAN8700C-AEZG
PDF下载: 下载PDF文件 查看货源
内容描述: [LAN Controller, 4 Channel(s), 12.5MBps, CMOS, 6 X 6 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, QFN-36]
分类和应用: 通信时钟局域网数据传输外围集成电路
文件页数/大小: 83 页 / 687 K
品牌: SMSC [ SMSC CORPORATION ]
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±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint  
Datasheet  
Table 5.46 Interrupt Management Table (continued)  
Mask  
30.5  
Interrupt Source Flag  
Remote Fault Detected  
Interrupt Source  
Remote Fault  
Event to Assert nINT  
Rising 1.4  
Event to De-Assert nINT  
29.5  
1.4  
Falling 1.4, or  
Reading register 1 or  
Reading register 29  
30.4  
30.3  
30.2  
29.4  
29.3  
29.2  
Link Down  
1.2  
5.14  
6.4  
Link Status  
Falling 1.2  
Rising 5.14  
Rising 6.4  
Reading register 1 or  
Reading register 29  
Auto-Negotiation LP  
Acknowledge  
Acknowledge  
Falling 5.14 or  
Read register 29  
Parallel Detection Fault  
Parallel Detection  
Fault  
Falling 6.4 or  
Reading register 6, or  
Reading register 29 or  
Re-Auto Negotiate or  
Link down  
30.1  
29.1  
Auto-Negotiation Page  
Received  
6.1  
Page Received  
Rising 6.1  
Falling of 6.1 or  
Reading register 6, or  
Reading register 29  
Re-Auto Negotiate, or  
Link Down.  
a.  
If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert for  
256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an  
unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the  
ENERGYON interrupt service routine.  
Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,  
therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is  
present, then both 17.1 and 29.7 will clear within a few milliseconds.  
5.3.2  
Alternate Interrupt System  
The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).  
To set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 5.47).  
To Clear an interrupt, either clear the corresponding bit in the Mask Register (30), this will de-assert  
the nINT output, or Clear the Interrupt Source, and write a ‘1’ to the corresponding Interrupt Source  
Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the Interrupt  
Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the Condition to De-  
Assert is true, then the Interrupt Source Flag is cleared, and the nINT is also de-asserted. If the  
Condition to De-Assert is false, then the Interrupt Source Flag remains set, and the nINT remains  
asserted.  
For example 30.7 is set to ‘1’ to enable the ENERGYON interrupt. After a cable is plugged in,  
ENERGYON (17.1) goes active and nINT will be asserted low.  
Revision 2.3 (04-12-11)  
SMSC LAN8700/LAN8700i  
DATA5S0HEET