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LAN8700C-AEZG 参数 Datasheet PDF下载

LAN8700C-AEZG图片预览
型号: LAN8700C-AEZG
PDF下载: 下载PDF文件 查看货源
内容描述: [LAN Controller, 4 Channel(s), 12.5MBps, CMOS, 6 X 6 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, QFN-36]
分类和应用: 通信时钟局域网数据传输外围集成电路
文件页数/大小: 83 页 / 687 K
品牌: SMSC [ SMSC CORPORATION ]
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±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint  
Datasheet  
Table 5.45 Register 31 - PHY Special Control/Status (continued)  
NAME DESCRIPTION  
ADDRESS  
MODE DEFAULT  
31.4:2  
Speed Indication  
HCDSPEED value:  
RO  
XXX  
[001]=10Mbps Half-duplex  
[101]=10Mbps Full-duplex  
[010]=100Base-TX Half-duplex  
[110]=100Base-TX Full-duplex  
31.1  
31.0  
Reserved  
Write as 0; ignore on Read  
RW  
RW  
0
0
Scramble Disable  
0 = enable data scrambling  
1 = disable data scrambling,  
5.3  
Interrupt Management  
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3  
specification. It generates an active low asynchronous interrupt signal on the nINT output whenever  
certain events are detected as setup by the Interrupt Mask Register 30.  
The Interrupt system on the SMSC LAN8700/8700I has two modes, a Primary Interrupt mode and an  
Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask  
bit is set, the difference is how they de-assert the output interrupt signal nINT.  
The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative  
interrupt mode would need to be setup again after a power-up or hard reset.  
5.3.1  
Primary Interrupt System  
The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt  
System is always selected after power-up or hard reset.  
To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5.46).  
Then when the event to assert nINT is true, the nINT output will be asserted.  
When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.  
Table 5.46 Interrupt Management Table  
Mask  
Interrupt Source Flag  
ENERGYON  
Interrupt Source  
ENERGYON  
Event to Assert nINT  
Rising 17.1a  
Event to De-Assert nINT  
30.7  
30.6  
29.7  
29.6  
17.1  
1.5  
Falling 17.1 or  
Reading register 29  
Auto-Negotiation  
complete  
Auto-Negotiate  
Complete  
Rising 1.5  
Falling 1.5 or  
Reading register 29  
SMSC LAN8700/LAN8700i  
Revision 2.3 (04-12-11)  
DATA4S9HEET  
 
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