High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
5.4.9.2
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block.
Table 5.53 MODE[2:0] Bus
DEFAULT REGISTER BIT VALUES
MODE[2:0]
MODE DEFINITIONS
REGISTER 0
[13,12,10,8]
REGISTER 4
[8,7,6,5]
000
001
010
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
0000
0001
1000
N/A
N/A
N/A
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
011
100
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
1001
1100
N/A
100ase-TX Half Duplex is advertised. Auto-
negotiation enabled.
0100
CRS is active during Transmit & Receive.
101
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
1100
0100
110
111
Power Down mode. In this mode the PHY wake-up
in Power-Down mode.
N/A
N/A
All capable. Auto-negotiation enabled.
X10X
1111
5.5
Analog
The analog blocks of the chip are described in this section.
5.5.1
ADC
The ADC is a 6 bit 125 MHz sample rate Analog to Digital Converter designed to serve as the analog
front end of a digital 100Base-Tx receiver.
5.5.1.1
Functional Description
The ADC has a full flash architecture for maximum speed and minimum latency. An internally
generated 125MHz clock is used to time the sampling and processing.
The ADC has a variable gain, which is controlled by the DSP block. This allows accurate A/D
conversion over the entire range of input signal amplitudes, which is particularly important for lower
amplitude signals (longer cables).
INPUT COMMON MODE
The differential input is applied to the RXP/N signals. For proper operation of the ADC the input
common mode should match the internal differential reference common mode. To achieve this, the
ADC generates the appropriate voltage and drives it via the VCOM signal.
Rev. 0.6 (12-12-03)
SMSC LAN83C185
DATA4S2HEET
SMSC [ SMSC CORPORATION ]
