USB2.0 PHY IC
CLK60
RXACTIVE
RXDATA[7:0]
PID
DATA
CRC
CRC
DATA
DATA
DATA
RXVALID
RXERROR
DP/DM
PID
DATA
CRC
CRC
SYNC
DATA
DATA
DATA
EOP
CRC-16 Computation
Figure 7.12 Receive Timing for Data Packet with CRC-16 (8-bit mode)
7.6
7.7
FS/HS RX
The receivers connect directly to the USB cable. The block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE.
For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.
FS/HS TX
The transmitters connect directly to the USB cable. The block contains a separate differential FS and
HS transmitter which receive encoded, bitstuffed, serialized data from the TX Logic block and transmit
it on the USB cable. The FS/HS TX block also contains circuitry that either enables or disables the
pull-up resistor on the D+ line.
7.8
7.9
Biasing
This block consists of an internal bandgap reference circuit used for generating the driver current and
the biasing of the analog circuits. This block requires an external precision resistor (12kΩ +/- 1% from
the RBIAS pin to analog ground).
Power Control
This is the block that receives and distributes all the power for the transceiver. This block is also
responsible for handling ESD protection.
SMSC GT3200, SMSC USB3250
Revision 1.3 (10-05-04)
DATA2S6HEET
SMSC [ SMSC CORPORATION ]
