USB2.0 PHY IC
Note 7.2 Figure 7.10, Figure 7.11 and Figure 7.12 are timing examples of a HS/FS Macrocell when
it is in HS mode. When a HS/FS Macrocell is in FS Mode (8-bit mode) there are
approximately 40 CLK60 cycles every byte time. The Receive State Machine assumes that
the SIE captures the data on the RXDATA bus if RXACTIVE and RXVALID are asserted.
In FS mode, RXVALID will only be asserted for one CLK60 per byte time.
Note 7.3 Figure 7.10, Figure 7.11 and Figure 7.12 the SYNC pattern on DP/DM is shown as one
byte long. The SYNC pattern received by a device can vary in length. These figures
assume that all but the last 12 bits have been consumed by the hubs between the device
and the host controller.
CLK60
RXACTIVE
PID
RXDATA[7:0]
RXVALID
RXERROR
DP/DM
SYNC
PID
EOP
Figure 7.10 Receive Timing for Data (with CRC-16 in 8-bit mode)
CLK60
RXACTIVE
PID
DATA
DATA
RXDATA[7:0]
RXVALID
RXERROR
DP/DM
SYNC
PID
DATA
DATA
EOP
CRC-5 Computation
Figure 7.11 Receive Timing for Setup Packet (8-bit mode)
Revision 1.3 (10-05-04)
SMSC GT3200, SMSC USB3250
DATA2S5HEET
SMSC [ SMSC CORPORATION ]
