USB2.0 PHY IC
CLK60
RXACTIVE
Invalid Data
DATA
DATA
DATA
DATA
Data
RXDATA[7:0]
Invalid
Invalid
CRC
CRC
DATA
RXVALID
Figure 7.7 Receive Timing for Data with Unstuffed Bits (8-bit mode)
CLK30
RXVALID
VALIDH
DATA[7:0]
DATA[15:8]
PID
DATA
DATA (3)
DATA (4)
CRC (LO)
CRC (HI)
(1)
DATA (0)
DATA (2)
RXACTIVE
DP/DM
SYNC
PID
DATA DATA DATA DATA DATA CRC
LO
CRC
HI
EOP
0
1
2
3
4
Figure 7.8 Receive Timing for 16-bit Data, Even Byte Count
Revision 1.3 (10-05-04)
SMSC GT3200, SMSC USB3250
DATA2S3HEET