6. The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin
the termination phase of the cycle.
7. When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
Table 40 - EPP Pin Descriptions
EPP
SIGNAL
EPP NAME
nWrite
TYPE
EPP DESCRIPTION
nWRITE
PD<0:7>
INTR
O
I/O
I
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
Address/Data
Interrupt
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP.)
WAIT
nWait
I
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data
is completed. It is driven active as an indication that the
device is ready for the next transfer.
DATASTB nData Strobe
RESET nReset
O
O
O
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
ADDRSTB nAddress
Strobe
This signal is active low. It is used to denote address read
or write operation.
PE
Paper End
I
I
Same as SPP mode.
Same as SPP mode.
SLCT
Printer
Selected
Status
nERR
PDIR
Error
I
Same as SPP mode.
Parallel Port
Direction
O
This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and
a high means an input/read condition. This signal is
normally a low (output/write) unless PCD of the control
register is set or if an EPP read cycle is in progress.
Note 1: SPP and EPP can use one common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP
cycle. For correct EPP read cycles, PCD is required to be a low.
94
SMSC [ SMSC CORPORATION ]
