The transmitter interrupt after changing
FCR0 will be immediate, if it is enabled.
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·
BIT 0=1 as long as there is one byte in the
RCVR FIFO.
BITS 1-4 specify which error(s) have
occurred. Character error status is handled
the same way as when in the interrupt
mode, the IIR is not affected since EIR bit
2=0.
BIT 5 indicates when the XMIT FIFO is
empty.
BIT 6 indicates that both the XMIT FIFO
and shift register are empty.
Character timeout and RCVR FIFO trigger level
interrupts have the same priority as the current
received data available interrupt; XMIT FIFO
empty has the same priority as the current
transmitter holding register empty interrupt.
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FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
BIT 7 indicates whether there are any errors
in the RCVR FIFO.
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
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