two is loaded the output is a divide by 2 signal
with a 50% duty cycle. If a 3 or greater is
loaded the output is low for 2 bits and high for
the remainder of the count. The input clock to
the BRG is a 1.8462 MHz clock.
·
·
at least one character is in the FIFO
The most recent serial character
received was longer than four
continuous character times ago. (If 2
stop bits are programmed, the second
one is included in this time delay.)
The most recent CPU read of the FIFO
was longer than four continuous
character times ago.
Table 34 shows the baud rates possible with a
1.8462 MHz crystal.
·
Effect Of The Reset on Register File
This will cause a maximum character received
to interrupt issued delay of 160 msec at 300
BAUD with a 12 bit character.
The Reset Function Table (Table 34) details the
effect of the Reset input on each of the registers
of the Serial Port.
B. Character times are calculated by using the
RCLK input for a clock signal (this makes
the delay proportional to the baudrate).
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts
are enabled (FCR bit 0 = "1", IER bit 0 = "1"),
RCVR interrupts occur as follows:
C. When a timeout interrupt has occurred it is
cleared and the timer reset when the CPU
reads one character from the RCVR FIFO.
A. The receive data available interrupt will be
issued when the FIFO has reached its
programmed trigger level; it is cleared as
soon as the FIFO drops below its
programmed trigger level.
D. When a timeout interrupt has not occurred
the timeout timer is reset after a new
character is received or after the CPU reads
the RCVR FIFO.
B. The IIR receive data available indication also
occurs when the FIFO trigger level is
reached. It is cleared when the FIFO drops
below the trigger level.
When the XMIT FIFO and transmitter interrupts
are enabled (FCR bit 0 = "1", IER bit 1 = "1"),
XMIT interrupts occur as follows:
A. The transmitter holding register interrupt
(02H) occurs when the XMIT FIFO is
empty; it is cleared as soon as the
transmitter holding register is written to (1
of 16 characters may be written to the XMIT
FIFO while servicing this interrupt) or the
IIR is read.
C. The receiver line status interrupt (IIR=06H),
has higher priority than the received data
available (IIR=04H) interrupt.
D. The data ready bit (LSR bit 0) is set as soon
as a character is transferred from the shift
register to the RCVR FIFO. It is reset when
the FIFO is empty.
B. The transmitter FIFO empty indications will
be delayed 1 character time minus the last
stop bit time whenever the following occurs:
THRE=1 and there have not been at least
two bytes at the same time in the
transmitter FIFO since the last THRE=1.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts occur
as follows:
A. A FIFO timeout interrupt occurs if all the
following conditions exist:
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