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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
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SERIAL PORT (UART)  
The FDC37C93xFR incorporates two full  
function UARTs. They are compatible with the  
NS16450, the 16450 ACE registers and the  
"1". OUT2 being a logic "0" disables that  
UART's interrupt. The second UART also  
supports IrDA, HP-SIR, ASK-IR, Fast IR and  
Consumer IR infrared modes of operation.  
NS16550A.  
parallel conversion on received characters and  
parallel-to-serial conversion on transmit  
The UARTS perform serial-to-  
Note: The UARTs may be configured to share  
an interrupt. Refer to the Configuration section  
for more information.  
characters. The data rates are independently-  
programmable from 460.8K baud down to 50  
baud. The character options are programmable  
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky  
or no parity; and prioritized interrupts. The  
UARTs each contain a programmable baud rate  
generator that is capable of dividing the input  
clock or crystal by a number from 1 to 65535.  
The UARTs are also capable of supporting the  
MIDI data rate. Refer to the Configuration  
Registers for information on disabling, power  
down and changing the base address of the  
UARTs. The interrupt from a UART is enabled  
by programming, OUT2 of that UART to a logic  
REGISTER DESCRIPTION  
Addressing of the accessible registers of the  
Serial Port is shown below.  
The base  
addresses of the serial ports are defined by the  
configuration registers (see Configuration  
section). The Serial Port registers are located at  
sequentially increasing addresses above these  
base addresses. The FDC37C93xFR contains  
two serial ports, each of which contain a register  
set as described below.  
Table 32 - Addressing the Serial Port  
DLAB*  
A2  
0
0
0
0
0
0
1
1
1
1
0
0
A1  
0
0
0
1
1
1
0
0
1
1
0
0
A0  
0
0
1
0
0
1
0
1
0
1
0
1
REGISTER NAME  
Receive Buffer (read)  
0
0
Transmit Buffer (write)  
0
Interrupt Enable (read/write)  
Interrupt Identification (read)  
FIFO Control (write)  
X
X
X
X
X
X
X
1
Line Control (read/write)  
Modem Control (read/write)  
Line Status (read/write)  
Modem Status (read/write)  
Scratchpad (read/write)  
Divisor LSB (read/write)  
Divisor MSB (read/write)  
1
*NOTE: DLAB is Bit 7 of the Line Control Register  
69  
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