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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 31 - Effects of WGATE and GAP Bits  
LENGTH OF  
GAP2 FORMAT  
FIELD  
PORTION OF GAP 2  
WRITTEN BY WRITE  
DATA OPERATION  
WGATE  
GAP  
MODE  
0
0
0
1
Conventional  
Perpendicular  
(500 Kbps)  
Reserved  
(Conventional)  
Perpendicular  
(1 Mbps)  
22 Bytes  
22 Bytes  
0 Bytes  
19 Bytes  
1
1
0
1
22 Bytes  
41 Bytes  
0 Bytes  
38 Bytes  
LOCK  
ENHANCED DUMPREG  
In order to protect systems with long DMA  
latencies against older application software that  
can disable the FIFO, the LOCK Command has  
been added. This command should only be  
used by the FDC routines, and application  
software should refrain from using it. If an  
application calls for the FIFO to be disabled  
then the CONFIGURE command should be  
used.  
The DUMPREG command is designed to  
support system run-time diagnostics and  
application software development and debug.  
To accommodate the LOCK command and the  
enhanced PERPENDICULAR MODE command  
the eighth byte of the DUMPREG command has  
been modified to contain the additional data  
from these two commands.  
COMPATIBILITY  
The LOCK command defines whether the  
EFIFO, FIFOTHR, and PRETRK parameters of  
the CONFIGURE command can be RESET by  
the DOR and DSR registers. When the LOCK  
bit is set to logic "1" all subsequent "software  
RESETS by the DOR and DSR registers will not  
change the previously set parameters to their  
default values. All "hardware" RESET from the  
RESET pin will set the LOCK bit to logic "0" and  
return the EFIFO, FIFOTHR, and PRETRK to  
their default values. A status byte is returned  
immediately after issuing a a LOCK command.  
This byte reflects the value of the LOCK bit set  
by the command byte.  
The FDC37C93xFR was designed with software  
compatibility in mind. It is a fully backwards-  
compatible solution with the older generation  
765A/B disk controllers.  
implements on-board registers for compatibility  
with the PS/2, as well as PC/AT and PC/XT,  
The FDC also  
floppy disk controller subsystems. After  
a
hardware reset of the FDC, all registers,  
functions and enhancements default to a PC/AT,  
PS/2 or PS/2 Model 30 compatible operating  
mode, depending on how the IDENT and MFM  
bits are configured by the system BIOS.  
68  
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