欢迎访问ic37.com |
会员登录 免费注册
发布采购

FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号FDC37CXFR的Datasheet PDF文件第34页浏览型号FDC37CXFR的Datasheet PDF文件第35页浏览型号FDC37CXFR的Datasheet PDF文件第36页浏览型号FDC37CXFR的Datasheet PDF文件第37页浏览型号FDC37CXFR的Datasheet PDF文件第39页浏览型号FDC37CXFR的Datasheet PDF文件第40页浏览型号FDC37CXFR的Datasheet PDF文件第41页浏览型号FDC37CXFR的Datasheet PDF文件第42页  
The FDC activates the FDRQ pin when entering  
the execution phase of the data transfer  
commands. The DMA controller must respond  
by activating the nDACK and nIOW pins and  
placing data in the FIFO. FDRQ remains active  
until the FIFO becomes full. FDRQ is again set  
true when the FIFO has <threshold> bytes  
remaining in the FIFO. The FDC will also  
deactivate the FDRQ pin when TC becomes true  
(qualified by nDACK), indicating that no more  
data is required. FDRQ goes inactive after  
nDACK goes active for the last byte of a data  
transfer (or on the active edge of nIOW of the  
last byte, if no edge is present on nDACK). A  
data overrun may occur if FDRQ is not removed  
in time to prevent an unwanted cycle.  
received. The only difference between these  
implicit functions and TC is that they return  
"abnormal termination" result status.  
Such  
status indications can be ignored if they were  
expected.  
Note that when the host is sending data to the  
FIFO of the FDC, the internal sector count will  
be complete when the FDC reads the last byte  
from its side of the FIFO. There may be a delay  
in the removal of the transfer request signal of  
up to the time taken for the FDC to read the last  
16 bytes from the FIFO. The host must tolerate  
this delay.  
Result Phase  
Data Transfer Termination  
The generation of FINT determines the  
beginning of the result phase. For each of the  
commands, a defined set of result bytes has to  
be read from the FDC before the result phase is  
complete. These bytes of data must be read out  
for another command to start.  
The FDC supports terminal count explicitly  
through the TC pin and implicitly through the  
underrun/overrun and end-of-track (EOT)  
functions. For full sector transfers, the EOT  
parameter can define the last sector to be  
transferred in a single or multi-sector transfer.  
RQM and DIO must both equal "1" before the  
result bytes may be read. After all the result  
bytes have been read, the RQM and DIO bits  
switch to "1" and "0" respectively, and the CB bit  
is cleared, indicating that the FDC is ready to  
accept the next command.  
If the last sector to be transferred is a partial  
sector, the host can stop transferring the data in  
mid-sector, and the FDC will continue to  
complete the sector as if a hardware TC was  
38  
 复制成功!