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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
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FIFO. The data is based upon the following  
formula:  
DATA REGISTER (FIFO)  
Address 3F5 READ/WRITE  
Threshold # x  
1
x 8  
- 1.5 ms = DELAY  
All command parameter information, disk data  
and result status are transferred between the  
host processor and the floppy disk controller  
through the Data Register.  
DATA RATE  
At the start of a command, the FIFO action is  
always disabled and command parameters  
must be sent based upon the RQM and DIO bit  
settings. As the command execution phase is  
entered, the FIFO is cleared of any data to  
ensure that invalid data is not transferred.  
Data transfers are governed by the RQM and  
DIO bits in the Main Status Register.  
The Data Register defaults to FIFO disabled  
mode after any form of reset. This maintains  
PC/AT hardware compatibility.  
values can be changed through the Configure  
command (enable full FIFO operation with  
threshold control). The advantage of the FIFO  
is that it allows the system a larger DMA latency  
without causing a disk error. Table 15 gives  
several examples of the delays with a  
An overrun or underrun will terminate the  
current command and the transfer of data. Disk  
writes will complete the current sector by  
generating a 00 pattern and valid CRC. Reads  
require the host to remove the remaining data  
so that the result phase may be entered.  
The default  
Table 15 - FIFO Service Delay  
FIFO THRESHOLD  
EXAMPLES  
MAXIMUM DELAY TO SERVICING AT 2  
Mbps* DATA RATE  
1 byte  
2 bytes  
8 bytes  
15 bytes  
1 x 4 ms - 1.5 ms = 2.5 ms  
2 x 4 ms - 1.5 ms = 6.5 ms  
8 x 4 ms - 1.5 ms = 30.5 ms  
15 x 4 ms - 1.5 ms = 58.5 ms  
FIFO THRESHOLD  
EXAMPLES  
MAXIMUM DELAY TO SERVICING AT 1  
Mbps DATA RATE  
1 byte  
2 bytes  
8 bytes  
15 bytes  
1 x 8 ms - 1.5 ms = 6.5 ms  
2 x 8 ms - 1.5 ms = 14.5 ms  
8 x 8 ms - 1.5 ms = 62.5 ms  
15 x 8 ms - 1.5 ms = 118.5 ms  
FIFO THRESHOLD  
EXAMPLES  
MAXIMUM DELAY TO SERVICING AT  
500 Kbps DATA RATE  
1 byte  
2 bytes  
8 bytes  
15 bytes  
1 x 16 ms - 1.5 ms = 14.5 ms  
2 x 16 ms - 1.5 ms = 30.5 ms  
8 x 16 ms - 1.5 ms = 126.5 ms  
15 x 16 ms - 1.5 ms = 238.5 ms  
*The 2 Mbps data rate is only available if VCC = 5V.  
28  
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