The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic “1” indicates a paper end;
a logic “0” indicates the presence of paper.
BIT 6 nACK - nACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the
printer has received a character and can now accept another. A logic “1” means that it is still processing the last
character or has not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0
in this bit means that the printer is busy and cannot accept a new character. A logic “1” means that it is ready to
accept the next character.
CONTROL PORT
ADDRESS OFFSET = 02H
The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized by the
RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
BIT 1 AUTOFD – AUTOFEED
This bit is inverted and output onto the nAUTOFD output. A logic “1” causes the printer to generate a line feed
after each line is printed. A logic 0 means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN output. A logic “1” on this bit selects the printer; a logic “0” means
the printer is not selected.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel
Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the
IRQE bit is programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is valid in extended mode only (CR#1<3>=0). In printer mode, the direction is always out
regardless of the state of this bit. In bi-directional mode, a logic “0” means that the printer port is in output mode
(write); a logic “1” means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is cleared at
initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output
onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed,
the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 -
PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data
output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This
register is only available in EPP mode.
SMSC DS – FDC37N3869
Page 72
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
