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FDC37M607 参数 Datasheet PDF下载

FDC37M607图片预览
型号: FDC37M607
PDF下载: 下载PDF文件 查看货源
内容描述: 增强的超级I / O控制器,红外支持 [ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT]
分类和应用: 控制器
文件页数/大小: 182 页 / 634 K
品牌: SMSC [ SMSC CORPORATION ]
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reverse: Peripheral to Host communication  
Pword: A port word; equal in size to the width  
of the ISA interface. For this  
implementation, PWord is always 8  
bits.  
EXTENDED CAPABILITIES PARALLEL PORT  
ECP provides a number of advantages, some of  
which are listed below. The individual features  
are explained in greater detail in the remainder  
of this section.  
1
0
A high level.  
A low level.  
·
·
·
High performance half-duplex forward and  
reverse channel  
Interlocked handshake, for fast reliable  
transfer  
Optional single byte RLE compression for  
improved throughput (64:1)  
Channel addressing for low-cost peripherals  
Maintains link and data layer separation  
Permits the use of active output drivers  
Permits the use of adaptive signal timing  
Peer-to-peer capability  
These terms may be considered synonymous:  
·
·
·
·
·
·
·
·
·
·
PeriphClk, nAck  
HostAck, nAutoFd  
PeriphAck, Busy  
nPeriphRequest, nFault  
nReverseRequest, nInit  
nAckReverse, PError  
Xflag, Select  
ECPMode, nSelectln  
HostClk, nStrobe  
·
·
·
·
·
Vocabulary  
The following terms are used in this document:  
Reference Document: IEEE 1284 Extended  
Capabilities Port Protocol and ISA Interface  
assert: When a signal asserts it transitions to a  
"true" state, when a signal deasserts it  
transitions to a "false" state.  
Standard, Rev 1.14, July 14, 1993.  
document is available from Microsoft.  
This  
forward: Host to Peripheral communication.  
The bit map of the Extended Parallel Port  
registers is:  
D7  
PD7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Note  
data  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
ecpAFifo  
dsr  
Addr/RLE  
nBusy  
0
Address or RLE field  
2
1
1
2
2
2
nAck  
0
PError  
Select  
ackIntEn  
nFault  
0
0
0
dcr  
Direction  
SelectIn  
nInit  
autofd  
strobe  
cFifo  
ecpDFifo  
tFifo  
Parallel Port Data FIFO  
ECP Data FIFO  
Test FIFO  
cnfgA  
cnfgB  
ecr  
0
0
0
1
0
0
0
0
compress  
intrValue  
MODE  
Parallel Port IRQ  
nErrIntrEn  
Parallel Port DMA  
dmaEn  
serviceIntr  
full  
empty  
Note 1: These registers are available in all modes.  
Note 2: All FIFOs use one common 16 byte FIFO.  
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the  
Configuration Registers.  
89  
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