Table 56 - I/O Base Address Configuration Register Description
BASE I/O
LOGICAL
DEVICE LOGICAL REGISTER
RANGE
(NOTE3)
FIXED
BASE OFFSETS
NUMBER DEVICE
INDEX
0x00
FDC
0x60,0x61
[0x100:0x0FF8]
+0 : SRA
+1 : SRB
(Note 4)
ON 8 BYTE BOUNDARIES +2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
0x03
Parallel
Port
0x60,0x61
[0x100:0x0FFC]
ON 4 BYTE BOUNDARIES +1 : Status
+0 : Data|ecpAfifo
(EPP Not supported)
or
+2 : Control
+3 : EPP Address
+4 : EPP Data 0
[0x100:0x0FF8]
ON 8 BYTE BOUNDARIES +5 : EPP Data 1
(all modes supported, +6 : EPP Data 2
EPP is only available when +7 : EPP Data 3
the base address is on an 8- +400h : cfifo|ecpDfifo|tfifo
byte boundary)
|cnfgA
+401h : cnfgB
+402h : ecr
0x04
0x05
Serial Port 0x60,0x61
1
[0x100:0x0FF8]
+0 : RB/TB|LSB div
+1 : IER|MSB div
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Serial Port 0x60,0x61
2
[0x100:0x0FF8]
+0 : RB/TB|LSB div
+1 : IER|MSB div
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x62,0x63
Reserved
[0x100:0x0FF8]
ON 8 BYTE BOUNDARIES
0x06
133
SMSC [ SMSC CORPORATION ]
