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FDC37C669FRTQFP 参数 Datasheet PDF下载

FDC37C669FRTQFP图片预览
型号: FDC37C669FRTQFP
PDF下载: 下载PDF文件 查看货源
内容描述: [Floppy Disk Drive, 0.25MBps, IDE Compatible, CMOS, PQFP100, TQFP-100]
分类和应用: 驱动器存储微控制器和处理器次级存储控制器外围集成电路数据传输PC
文件页数/大小: 164 页 / 575 K
品牌: SMSC [ SMSC CORPORATION ]
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been initialized to 01H. The default value of this  
register after power up is 9CH.  
CR01  
This register can only be accessed in the  
Configuration Mode and after the CSR has  
Table 48 - CR01  
BIT NO.  
BIT NAME  
Reserved  
Parallel Port  
Power (see note (Default). A low level on this bit puts the Parallel Port in low  
DESCRIPTION  
Read Only. A read returns a 0.  
A high level on this bit, supplies power to the Parallel Port  
0,1  
2
_PWRDN)  
power mode.  
3
Parallel Port  
Mode  
Parallel Port Mode. A high level on this bit, sets the Parallel Port  
for Printer Mode (Default). A low level on this bit enables the  
Extended Parallel port modes. Refer to Bits 0 and 1 of CR4  
4
5,6  
7
Reserved  
Reserved  
Lock CRx  
Read Only. A read returns a 1.  
Read Only. A read returns a 0.  
A high level on this bit enables the reading and writing of CR00-  
CR18 (Default). A low level on this bit disables the reading and  
writing of CR0-CRF. Once set to 0, this bit can only be set to 1  
by a hard reset or power-up reset.  
initialized to 02H. The default value of this  
CR02  
This register can only be accessed in the  
register after power up is 88H.  
Configuration Mode and after the CSR has been  
Table 49 - CR02  
BIT NO.  
BIT NAME  
Reserved  
DESCRIPTION  
0:2  
3
Read Only. A read returns a 0.  
UART1 Power  
down (see note  
_PWRDN)  
A high level on this bit, allows normal operation of the Primary  
Serial Port (Default). A low level on this bit places the Primary  
Serial Port into Power Down Mode.  
4:6  
7
Reserved  
Read Only. A read returns a 0.  
UART2 Power  
down  
A high level on this bit, allows normal operation of the Secondary  
Serial Port (Default). A low level on this bit places the Secondary  
Serial Port into Power Down Mode.  
Note_PWRDN: Power Down bits disable the respective logical device and associated pins, however  
the power down bit does not disable the selected address range registers for the  
logical device. To disable the host address registers the logical device's base  
address must be set below 100h. Therefore devices which are powered down, but  
still reside at a valid I/O base address will participate in Plug-and-Play range  
checking.  
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