Table 60 - UART Interrupt Operation Table
UART2
UART1
UART1 IRQ
IRQ PINS
UART1
OUT2 bit
UART2
OUT2 bit
UART2 IRQ Output
State
UART1
UART2
Output State
Z
Share IRQ
No
Pin State
Pin State
0
1
1
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
Z
Z
1
0
Z
Z
1
1
0
0
Z
1
0
1
0
1
1
1
0
Z
Z
Z
1
0
1
0
1
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
asserted
de-asserted
Z
Z
Z
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
asserted
de-asserted
asserted
de-asserted
asserted
de-asserted
Z
Z
asserted
asserted
de-asserted
de-asserted
Z
asserted
de-asserted
Z
Z
Z
asserted
de-asserted
asserted
de-asserted
asserted
de-asserted
Z
asserted
asserted
de-asserted
de-asserted
It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential
damage to chip may result.
135
SMSC [ SMSC CORPORATION ]
