Command/Data
The most significant bit of the command indicates
whether it is a run-length count (for compression) or a
channel address.
ECP Mode supports two advanced features to improve
the effectiveness of the protocol for some applications.
The features are implemented by allowing the transfer of
normal 8-bit data or 8-bit commands.
When in the reverse direction, normal data is transferred
when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant
bit of the command is always zero. Reverse channel
addresses are seldom used and may not be supported in
hardware.
When in the forward direction, normal data is transferred
when HostAck is high and an 8 bit command is
transferred when HostAck is low.
Table 42
Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7
D[6:0]
0
Run-Length Count (0-127) (mode
0011 0X00 only)
1
Channel Address (0-127)
Data Compression
The FDC37C669 supports run length encoded (RLE)
decompression in hardware and can transfer compressed
indicates that the next byte should be expanded to 128
bytes. To prevent data expansion, however, run-length
counts of zero should be avoided.
data to
a peripheral. Run length encoded (RLE)
compression in hardware is not supported. To transfer
compressed data in ECP mode, the compression count is
written to the ecpAFifo and the data byte is written to the
ecpDFifo.
Pin Definition
The drivers for nStrobe, nAutoFd, nInit and nSelectIn
are open-collector in mode 000 and are push-pull in all
other modes.
Compression is accomplished by counting identical bytes
and transmitting an RLE byte that indicates how many
times the next byte is to be repeated. Decompression
simply intercepts the RLE byte and repeats the following
byte the specified number of times. When a run-length
count is received from a peripheral, the subsequent data
byte is replicated the specified number of times. A
run-length count of zero specifies that only one byte of
data is represented by the next data byte, whereas a
ISA Connections
The interface can never stall causing the host to hang.
The width of data transfers is strictly controlled on an I/O
address basis per this specification. All FIFO-DMA
transfers are byte wide, byte aligned and end on a byte
boundary. (The PWord value can be obtained by reading
Configuration Register A, cnfgA, described in the next
section). Single byte wide transfers
run-length
count
of
127
104
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