Table 41 - Extended Control Register
MODE
R/W
000: Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are
used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will
not tri-state the output drivers in this mode.
001: PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the data
lines and reading the data register returns the value on the data lines and not the value in the
data register. All drivers have active pull-ups (push-pull).
010: Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the
FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that
this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).
011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo
and bytes written to the ecpAFifo are placed in a single FIFOand transmitted automatically to
the peripheral using ECP Protocol. In the reverse direction (direction is1) bytes are moved from
the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups
(push-pull).
100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register CR4. All drivers have active pull-ups (push-pull).
101: Reserved
110: Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted
on the parallel port. All drivers have active pull-ups (push-pull).
111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
102
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