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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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ACPI, Logical Device A  
TABLE 85 - ACPI, LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A]  
NAME  
REG INDEX  
DEFINITION  
STATE  
Sleep/Wake  
Configuration  
This register is used to configure the functionality of  
the SLP_EN bit and its associated logic, and the  
WAK_STS bit bit and its associated logic. It also  
contains the CIR PLL Power bit.  
0xF0  
C
Default = 0x00  
on Vbat POR  
Bit[0] SLP_CTRL. SLP_EN Bit Function.  
0=Default. Writing ‘1’ to the SLP_EN bit causes the  
system to sequence into the sleeping state associated  
with the SLP_TYPx fields.  
1=Writing ‘1’ to the SLP_EN bit does not cause the  
system to sequence into the sleeping state associated  
with the SLP_TYPx fields; instead an SMI is  
generated.  
Note: the SLP_EN_SMI bit in the SMI Status Register  
2 is set whenever ‘1’ is written to the SLP_EN bit; it is  
enabled to generate an SMI through bit[0] of this  
register.  
Bit[1] WAK_CTRL. WAK_STS Bit Function  
0=Default. The WAK_STS bit is set on the high-to-low  
transition of nPowerOn.  
1=The WAK_STS bit is set upon any enabled wakeup  
event and the high-to-low transition of nPowerOn.  
Bits[2:6] Reserved  
Bit[7]: CIR PLL Power.  
0=Default. The 32KHz clock PLL is unpowered  
1=The 32KHz clock PLL is running and can replace  
the 14.318MHz clock source for the CIR wakeup  
event.  
212  
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