NAME
REG INDEX
DEFINITION
= 0 Minutes (default)
STATE
Default = 0x00
= 1 Seconds
on Vcc POR or
Reset_Drv
Note: if the logical device's activate bit is not set then
bits 0 and 1 have no effect.
WDT_VAL
0xF2
Watch-dog Timer Time-out Value
Binary coded, units = minutes(default) or seconds,
selectable via Bit[7] of Reg 0xF1, LD 8.
0x00 Time out disabled
0x01 Time-out = 1 minute/second
.........
C
Default = 0x00
on Vcc POR or
Reset_Drv
0xFF Time-out = 255 minutes/seconds
WDT_CFG
0xF3
Watch-dog timer Configuration
Bit[0] Joy-stick Enable
C
Default = 0x00
=1WDT is reset upon an I/O read or write of the
Game Port
=0WDT is not affected by I/O reads or writes to the
Game Port.
on Vcc POR or
Reset_Drv
Bit[1] Keyboard Enable
=1WDT is reset upon a Keyboard interrupt.
=0WDT is not affected by Keyboard interrupts.
Bit[2] Mouse Enable
=1WDT is reset upon a Mouse interrupt
=0WDT is not affected by Mouse interrupts.
Bit[3] PWRLED Time-out enable
=1Enables the Power LED to toggle at a 1Hz rate with
50 percent duty cycle while the Watch-dog Status bit
is set.
=0Disables the Power LED toggle during Watch-dog
timeout status.
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = Invalid
0001 = IRQ1
0000 = Disable
WDT_CTRL
0xF4
Watch-dog timer Control
C
Bit[0] Watch-dog Status Bit, R/W
=1WD timeout occured
Default = 0x00
=0WD timer counting
Bit[1] Power LED Toggle Enable, R/W
=1Toggle Power LED at 1Hz rate with 50 percent duty
cycle. (1/2 sec. on, 1/2 sec. off)
=0Disable Power LED Toggle
Cleared by VTR
POR
Bit[2] Force Timeout, W
=1Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
209
SMSC [ SMSC CORPORATION ]
