Bit 1 of Port 92, the ALT_A20 signal, is used to
force nA20M to the CPU low for support of real
for all timing. A port signal of 0 drives the
output to 0. A port signal of 1 causes the port
enable signal to drive the output to 1 within 20-
30nsec. After several (# TBD) clocks, the port
enable goes away and the internal 90µA pull-up
maintains the output signal as 1.
mode compatible software.
This signal is
externally OR’ed with the A20GATE signal from
the keyboard controller and CPURST to control
the nA20M input of the CPU. Writing a 0 to bit 1
of the Port 92 Register forces ALT_A20 low.
ALT_A20 low drives nA20M to the CPU low, if
A20GATE from the keyboard controller is also
low. Writing a 1 to bit 1 of the Port 92 Register
forces ALT_A20 high. ALT_A20 high drives
nA20M to the CPU high, regardless of the state
of A20GATE from the keyboard controller.
Upon reset, this signal is driven low.
In 8042 mode, the pins can be programmed as
open drain. When programmed in open drain
mode, the port enables do not come into play. If
the port signal is 0 the output will be 0. If the
port signal is 1, the output tristates: an external
pull-up can pull the pin high, and the pin can be
shared i.e., P12 and nSMI can be externally tied
together. In 8042 mode, the pins cannot be
programmed as input nor inverted through the
GP configuration registers.
8042 P12 and P16 Functions
8042 functions P12 and P16 are implemented
as in a true 8042 part. Reference the 8042 spec
127
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