Table 42 - FDC Parallel Port Pins
CONNECTOR
QFP
CHIP PIN # SPP MODE PIN DIRECTION FDC MODE PIN DIRECTION
PIN #
1
83
68
69
70
71
72
73
74
75
80
79
78
77
82
81
66
67
nSTROBE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
(nDS0)
nINDEX
nTRK0
nWP
I/(O) Note1
2
3
PD0
I
PD1
I
4
PD2
I
5
PD3
nRDATA
nDSKCHG
-
I
6
PD4
I
7
PD5
-
8
PD6
(nMTR0)
-
I/(O) Note1
9
PD7
-
10
11
12
13
14
15
16
17
nACK
BUSY
PE
nDS1
O
O
O
O
O
O
O
O
I
nMTR1
nWDATA
nWGATE
DRVDEN0
nHDSEL
nDIR
I
SLCT
nALF
nERROR
nINIT
nSLCTIN
I
I/O
I
I/O
I/O
nSTEP
Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1.
105