Bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake to
the peripheral using the standard parallel port
protocol. Transfers to the FIFO are byte aligned.
This mode is only defined for the forward direction.
0 and emptying it a byte at a time until serviceIntr
is set. This may generate a spurious interrupt, but
will indicate that the threshold has been reached.
The readIntrThreshold can be determined by
setting the direction bit to 1 and filling the empty
tFIFO a byte at a time until serviceIntr is set. This
may generate a spurious interrupt, but will indicate
that the threshold has been reached.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Data bytes are always read from the head of tFIFO
regardless of the value of the direction bit. For
example if 44h, 33h, 22h is written to the FIFO,
then reading the tFIFO will return 44h, 33h, 22h in
the same order as was written.
Bytes written or DMAed from the system to this
FIFO, when the direction bit is 0, are transmitted
by a hardware handshake to the peripheral using
the ECP parallel port protocol. Transfers to the
FIFO are byte aligned.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
Data bytes from the peripheral are read under
automatic hardware handshake from ECP into this
FIFO when the direction bit is 1. Reads or DMAs
from the FIFO will return bytes of ECP data to the
system.
This register is a read only register. When read,
10H is returned. This indicates to the system that
this is an 8-bit implementation. (PWord = 1 byte)
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
Data bytes may be read, written or DMAed to or
from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the to
the parallel port lines using a hardware protocol
handshake. However, data in the tFIFO may be
displayed on the parallel port data lines.
BIT 7 compress
This bit is read only. During a read it is a low level.
This means that this chip does not support
hardware RLE compression. It does support
hardware de-compression!
The tFIFO will not stall when overwritten or
underrun. If an attempt is made to write data to a
full tFIFO, the new data is not accepted into the
tFIFO. If an attempt is made to read data from an
empty tFIFO, the last data byte is re-read again.
The full and empty bits must always keep track of
the correct FIFO state. The tFIFO will transfer data
at the maximum ISA rate so that software may
generate performance metrics.
BIT 6 intrValue
Returns the value on the ISA IRq line to determine
possible conflicts.
BITS [5:3] Parallel Port IRQ (read-only)
Refer to Table 39B.
BITS [2:0] Parallel Port DMA (read-only)
Refer to Table 39C.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
The FIFO size and interrupt threshold can be
determined by writing bytes to the FIFO and
checking the full and serviceIntr bits.
BITS 7,6,5
The writeIntrThreshold can be determined by
starting with a full tFIFO, setting the direction bit to
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
99
SMSC [ SMSC CORPORATION ]
