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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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EXTENDED CAPABILITIES PARALLEL PORT  
ECP provides a number of advantages, some of  
Pword: A port word; equal in size to the width of  
the ISA interface. For this  
which are listed below. The individual features are  
explained in greater detail in the remainder of this  
section.  
implementation, PWord is always 8 bits.  
A high level.  
1
0
A low level.  
High performance half-duplex forward and  
reverse channel  
Interlocked handshake, for fast reliable  
transfer  
Optional single byte RLE compression for  
improved throughput (64:1)  
Channel addressing for low-cost peripherals  
Maintains link and data layer separation  
Permits the use of active output drivers  
Permits the use of adaptive signal timing  
Peer-to-peer capability  
These terms may be considered synonymous:  
PeriphClk, nAck  
HostAck, nAutoFd  
PeriphAck, Busy  
nPeriphRequest, nFault  
nReverseRequest, nInit  
nAckReverse, PError  
Xflag, Select  
ECPMode, nSelectln  
HostClk, nStrobe  
Vocabulary  
The following terms are used in this document:  
Reference Document:  
Capabilities Port Protocol and ISA Interface  
IEEE 1284 Extended  
Standard, Rev 1.14, July 14, 1993.  
document is available from Microsoft.  
This  
assert: When a signal asserts it transitions to a  
"true" state, when a signal deasserts it  
transitions to a "false" state.  
forward: Host to Peripheral communication.  
reverse: Peripheral to Host communication  
The bit map of the Extended Parallel Port  
registers is:  
D7  
PD7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Note  
data  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
ecpAFifo  
dsr  
Addr/RLE  
nBusy  
0
Address or RLE field  
2
1
1
2
2
2
nAck  
0
PError  
Select  
ackIntEn  
nFault  
0
0
0
dcr  
Direction  
SelectIn  
nInit  
autofd  
strobe  
cFifo  
ecpDFifo  
tFifo  
Parallel Port Data FIFO  
ECP Data FIFO  
Test FIFO  
cnfgA  
cnfgB  
ecr  
0
0
0
1
0
0
0
0
compress  
intrValue  
MODE  
Parallel Port IRQ  
nErrIntrEn  
Parallel Port DMA  
dmaEn  
serviceIntr  
full  
empty  
Note 1: These registers are available in all modes.  
Note 2: All FIFOs use one common 16 byte FIFO.  
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration  
Registers.  
This specification describes the standard ISA  
interface to the Extended Capabilities Port (ECP).  
ISA IMPLEMENTATION STANDARD  
94  
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